The formation of conductive structures for use as contacts and interconnecting wiring is essential to the fabrication of integrated circuit devices. For example, metal silicides and metal germanides are useful for interconnecting wiring as they provide equivalent resistance per square to heavily doped silicon or germanium while occupying less chip real estate. Metal silicide interconnecting wiring is typically formed using conventional lithographic and metal deposition techniques, which are followed by an annealing step. See "IBM Technical Disclosure Bulletin," Vol. 13, No. 2 (Jul. 1970).
Methods for producing metal silicide contacts are also known. "IBM Technical Disclosure Bulletin," Vol. 22, No. 12 (May 1980), for example, discloses a method for forming platinum silicide contacts by laser annealing a platinum layer and an amorphous silicon substrate. U.S. Pat. No. 4,729,969, on the other hand, discloses metal silicide contact formation through contact holes opened in an insulator film.
Metal silicides are also useful as conducting passivation layers in certain integrated (IC) applications. See U.S. Pat. No. 4,761,386, which discloses the use of metal silicides in connection with wire bonding to contact pads of IC chips.
There is much interest today in fabrication methods for metal-insulator-semiconductor (MIS) structures which will allow IC chips with high degrees of three dimensional integration to be produced. In particular, epitaxial MIS structures are essential ingredients for three dimensional device integration. Research attention has focused on forming epitaxial insulation layers using cubic flourite structure fluorides such as BaF.sub.2 and CaF.sub.2, which exhibit very low lattice mismatches with, for example, (111) silicon. See "Insulating Epitaxial Films of BaF.sub.2, CaF.sub.2 and Ba.sub.x Ca.sub.1-x F.sub.2 Grown by MBE on InP Substrates," Journal of Crystal Growth, Vol. 60, No. 2 (Dec. 1980), pages 403-413. Even when epitaxial insulators can be formed, there is still the problem of forming epitaxial contacts on, for example, CaF.sub.2 /Si structures in order to achieve suitable three dimensional MIS structures. See "Epitaxial Metal/Insulator/Semiconductor Structure Using CaSi.sub.2 /CaF.sub.2 /Si," Research Reports, No. 302 (Jun. 1989).
It will be appreciated from a review of the various cited references that even when methods for fabricating epitaxial insulators and conductors are developed, these methods require the use of conventional multi-step processes, particularly wet lithographic processes, in order to fabricate the insulation layer and conductive structures. Thus, the conventional techniques are both costly and subject to misalignment errors.